Wednesday, February 16, 2011
ECL
The characteristics of ECL are as follows:
(1) The Logic levels are normally 8V (Logic 1) and -1.7 V (Logic O).
(2) The transistors never saturate, it, storage delay in ECL circuits is eliminated, and hence switching speed is very high.
(3) Because of the low noise margin, 250 milli-volt, ECL circuits are not reliable in heavy industrial environments.
(4) An ECH logic block usually produces an O/P and its complement. This eliminates need for invertors.
(5) Fan-outs are typically around 25, owing to the loco impedence mitter- follower O/PS.
(6) Typical power dissipation for a basic ECH gate is 40 ml somewhat higher than the 74AS series.
(7) The total current flow in an ECH circuit remains relatively constant regardlers of its logic states.
Study the circuit and let me know if ECLis fastest or not and if yes then why?
(1) The Logic levels are normally 8V (Logic 1) and -1.7 V (Logic O).
(2) The transistors never saturate, it, storage delay in ECL circuits is eliminated, and hence switching speed is very high.
(3) Because of the low noise margin, 250 milli-volt, ECL circuits are not reliable in heavy industrial environments.
(4) An ECH logic block usually produces an O/P and its complement. This eliminates need for invertors.
(5) Fan-outs are typically around 25, owing to the loco impedence mitter- follower O/PS.
(6) Typical power dissipation for a basic ECH gate is 40 ml somewhat higher than the 74AS series.
(7) The total current flow in an ECH circuit remains relatively constant regardlers of its logic states.
Study the circuit and let me know if ECLis fastest or not and if yes then why?
Toggle Flip flop
T-Flip- Flop: A T-Flip-Flop acts a toggle switch toggle means to switch over to the opposite state. It can be realized using a I-K flip flop by making T = I = K =1, as shown in the figure below:
Truth Table
Input Output
T Qn+1
O Qn
1 Qn
Why this is known as Toggle flip flop?
Truth Table
Input Output
T Qn+1
O Qn
1 Qn
Why this is known as Toggle flip flop?
Delay Flip Flop
D-Flip Flops: An S-R flip flop has 2 inputs, S & R. To store 1, a high S and low R an required. To stone O, a high R below S are needed. Thus, 2 signals an to be generated to draw an S-R flip flop. A D-flip-flop can be realized using an S-R flip- Flop as shown.
The truth table for D flip-flop is shown below:
Clk D Input Qn+1
0 X Qn (last state)
1 1 1
1 0 0
1 X Qn (last state)
Why this is known as a delay flip flop?
The truth table for D flip-flop is shown below:
Clk D Input Qn+1
0 X Qn (last state)
1 1 1
1 0 0
1 X Qn (last state)
Why this is known as a delay flip flop?
Thursday, February 3, 2011
Thought for the day
There are two kinds of failures:
those who thought and never did,
and those who did and never thought.
for more details log on http://www.gurukpo.com/
those who thought and never did,
and those who did and never thought.
for more details log on http://www.gurukpo.com/
Thought for the day
There are two kinds of failures:
those who thought and never did,
and those who did and never thought.
those who thought and never did,
and those who did and never thought.
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