D-Flip Flops: An S-R flip flop has 2 inputs, S & R. To store 1, a high S and low R an required. To stone O, a high R below S are needed. Thus, 2 signals an to be generated to draw an S-R flip flop. A D-flip-flop can be realized using an S-R flip- Flop as shown.
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The truth table for D flip-flop is shown below:
Clk D Input Qn+1
0 X Qn (last state)
1 1 1
1 0 0
1 X Qn (last state)
Why this is known as a delay flip flop?
The truth table for D flip-flop is shown below:
Clk D Input Qn+1
0 X Qn (last state)
1 1 1
1 0 0
1 X Qn (last state)
Why this is known as a delay flip flop?
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